1. Field of the Invention
The present invention relates to a test apparatus and a manufacturing method of a semiconductor memory. More specifically, the invention relates to a test apparatus for testing a memory-under-test such as a semiconductor memory and a manufacturing method for manufacturing a semiconductor memory into which a predetermined data pattern has been written.
2. Related Art
Conventionally, as an apparatus for testing a memory-under-test such as a semiconductor memory, there has been known an apparatus having means for writing a predetermined pattern into the memory-under-test and means for judging whether or not the pattern has been normally written into the memory-under-test. The memory-under-test has a plurality of storage blocks and the test apparatus judges whether or not each storage block is defect-free for example.
There is also a case when the test apparatus stores data used in a device for mounting the memory-under-test in the memory-under-test in advance. That is, there is a case when data used after shipping is written in advance into the memory-under-test to be shipped. Writing of such data is carried out by using the writing means described above.
As the writing means, the conventional test apparatus has a pattern memory for storing a predetermined pattern and means for generating an address of the pattern memory in which data to be written is stored and an address of the memory-under-test into which the data is to be written. At this time, the generated address of the memory-under-test converted into the address of the pattern memory is used as the address of the pattern memory generated by the address generating means.
However, if there exits a bad block in the memory-under-test, no data can be written into the bad block in storing the shipping pattern to the memory-under-test. The conventional test apparatus generates the address of the memory-under-test by correlating with the address of the pattern memory in one-to-one. Therefore, data corresponding to the bad block in the pattern to be written is written only to the bad block. Accordingly, it has been unable to utilize the data corresponding to the bad block after being written into the memory-under-test.
Therefore, the conventional test apparatus has written the pattern by selecting a memory-under-test having no bad block in advance in writing the shipping pattern into the memory-under-test. However, a yield of the test becomes worse by making such selection. Because a data amount of the pattern to be written has been increasing lately in particular, the yield of the test has worsened very much due to such selection.